This application claims priority from Korean Patent Application No. 2002-52728 filed on Sep. 3, 2002 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
The present invention relates to semiconductor memory devices and methods of fabrication therefor, and more particularly, to phase-changeable memory devices and methods of fabrication therefor.
Semiconductor memory devices can be categorized as either volatile memory devices or nonvolatile memory devices according to whether or not data is retained when power supplies are interrupted. The volatile memory devices may be classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM). The nonvolatile memory devices include flash memory devices. These memory devices represent a logic value, such as xe2x80x9c0xe2x80x9d or xe2x80x9c1,xe2x80x9d based on stored charge. Because a periodic refresh operation is typically needed for such devices, a DRAM may require a high charge storage capacitance. Consequently, there have been attempts to increase a surface area of a capacitor electrode to increase storage capacitance. However, an increase in the surface area of the capacitor electrode can interfere with an increase in integration of the DRAM.
A typical flash memory device has gate patterns including a gate insulating layer, a floating gate, a dielectric layer, and a control gate, which are sequentially stacked on a semiconductor substrate. To write and erase data, a method of tunneling charges through the gate insulating layer is used at a voltage that is higher than the normal power supply voltage. Accordingly, flash memory devices typically require a booster circuit in order to produce the voltage for erase and write operations.
As memory devices become highly integrated, many efforts have been underway to develop a new memory device having nonvolatile and random access characteristics, and a simple structure. Phase-changeable memory devices are one type of such memory devices. A typical phase-changeable memory device has a cell made of a phase-changeable material. Depending on a provided current density (i.e., Joule heating), the phase-changeable material can be electrically switched between amorphous and crystalline states and/or between variously resistive crystalline states.
FIG. 1 is a graph showing a method of programming and erasing a phase-changeable memory cell. Here, a horizontal axis represents time (T) and a vertical axis represents temperature (TMP: xc2x0 C.) applied to the phase-changeable material cell. The phase-changeable material is heated at a temperature that is higher than a melting temperature Tm during a relatively short first time T1. Next, the phase-changeable material is rapidly quenched. In this case, the phase-changeable material may be changed into the amorphous state (curve 1). During a second time T2 that is longer than the first time T1, the phase-changeable material is heated at a temperature that is lower than the melting temperature Tm and is higher than a crystallization temperature Tc. Next, the phase-changeable material is quenched. In this case, the phase-changeable material is changed into the crystalline state (curve 2). The resistivity of the phase-changeable material with the amorphous state is higher than that of the phase-changeable material with the crystalline state. Accordingly, currents flowing through the phase-changeable material may be detected in a read mode, and it is possible to discriminate whether information stored in the phase-changeable memory cell has a logic value of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Generally, a chalcogenide material is used as the phase-changeable material, in particular, a compound (hereinafter a xe2x80x9cGST layerxe2x80x9d) including germanium (Ge), stibium (Sb), and tellurium (Te).
As described above, heat is typically needed in order to switch the state of the phase-changeable material. In the typical phase-changeable memory device, if currents of a high density flow through an area contacting the phase-changeable material, a crystallization state of the phase-changeable material at a contact area is varied. The smaller the contact area is, the lower the current density for changing the state of the phase-changeable material.
FIG. 2 is a cross-sectional view for explaining a typical phase-changeable memory device structure, which schematically shows a phase-changeable memory cell. Referring to FIG. 2, the typical phase-changeable memory device includes a lower conductive pattern 10, a phase-changeable material pattern 16 and an upper conductive pattern 18. The phase-changeable material pattern 16 is electrically connected to the lower conductive pattern 10 through a contact plug 14 formed in an insulating layer 12. The insulating layer 12 is disposed on the lower conductive pattern 10. The upper conductive pattern 18 is formed on the phase-changeable material pattern 16. In the typical phase-changeable memory device, if currents flow between the lower conductive pattern 10 and the upper conductive pattern 18, the crystallization state of the phase-changeable material varies in accordance with a pulse (i.e., heat) of the currents flowing through an area (hereinafter referred to as xe2x80x9cactive contact areaxe2x80x9d) 20 where the contact plug 14 is in contact with the phase-changeable material pattern 16. The heat (i.e., energy) required to change the state of the phase-changeable material is directly affected by the active contact area 20 where the phase-changeable material pattern 16 is in contact with the contact plug 14. Preferably, the active contact area 20 should be made as small as possible.
However, because the lower conductive pattern 10 is connected to the phase-changeable material pattern 16 through the contact plug 14, a size of the active contact area 20 may be limited by a photolithography resolution for the contact hole, i.e., the size of the active contact area 20 generally cannot be reduced beyond the photolithography resolution. Furthermore, it may be difficult to form such contact holes uniformly in the memory device, which can result in variance in current flow for changing the state of the phase-changeable material for each contact area. Thus, mis-operation in read mode can easily occur. Also, because only one active contact area 20 is formed at the area that is in contact with the contact plug 14, a resistance variation resulting from the variation of the crystallization state is small.
According to some embodiments of the present invention, a phase-changeable memory device comprises a substrate and an access transistor formed in and/or on the substrate. Laterally spaced apart first and second conductive patterns are disposed on the substrate and have opposing sidewalls. A conductor electrically connects the first conductive region to a source/drain region of the access transistor. A phase-changeable material region is disposed between the first and second conductive patterns and contacts the opposing sidewalls of the first and second conductive patterns.
In some embodiments, the access transistor comprises first and second source/drain regions in the substrate and a gate electrode disposed on the substrate between the first and second source drain regions. The memory device further comprises an insulating layer disposed on the substrate and overlying the gate electrode and the first and second source/drain regions. The first and second conductive patterns are disposed on the insulating layer, and the conductor passes through the insulating layer and connects the first conductive pattern to the first source/drain region. The phase-changeable material layer is disposed on the insulating layer between the first and second conductive regions. The first and second conductive patterns may overlie respective ones of the first and second source/drain regions, and the phase-changeable material region may overlie the gate electrode.
According to further aspects, the conductor extends from the first source/drain region to contact the overlying first conductive pattern at a first contact area, and the first conductive pattern contacts the phase-changeable material region at a second contact area that is substantially smaller than the first contact area. The insulating layer may comprise a first insulating layer, the conductor may comprise a first conductor, and the memory device may further comprise a second insulating layer disposed on the substrate and overlying the first and second conductive patterns, and a second conductor passing through the second insulating layer and contacting the second conductive pattern at a third contact area. The second conductive pattern may contact the phase-changeable material region at a fourth contact area that is substantially smaller than the third contact area. For example, each of the first and second conductive patterns may comprise a body portion that contacts the corresponding one of the first and second conductors and a smaller tab portion that extends from the body portion to contact the phase-changeable material region.
A bit line conductor may be disposed on the second insulating layer, wherein the second conductor electrically connects the second conductive pattern to the bit line conductor. A common drain line conductor may be disposed in the first insulating layer between the second conductive pattern and the second source/drain region, and a third conductor may extend from the second source/drain region to contact the common drain line conductor.
According to further embodiments of the present invention, a phase-changeable memory device has active contact areas at opposite sidewalls of a phase-changeable material pattern. On the same plane as the phase-changeable material pattern, a pair of conductive patterns is disposed so as to be in contact with the active contact areas. Accordingly, a size of the active contact area depends on a thickness and a width of the conductive pattern. The thickness of the conductive patterns at the contact areas can be made smaller than the resolution of a photolithography resolution, so size of the active contact areas can be reduced in relation to conventional processes.
In accordance with further embodiments of the present invention, a phase-changeable memory device includes a pair of conductive patterns that are disposed on the same plane. The conductive patterns are spaced apart from each other. A variable resistivity material pattern is disposed between the conductive patterns so as to be in direct contact with the sidewalls of the conductive patterns at active contact areas. An upper metal interconnection for detecting resistivity of the variable resistivity material pattern is disposed over the conductive patterns and the variable resistivity material pattern so as to be electrically connected to one pattern of the conductive patterns. A semiconductor substrate having an impurity diffusion region is disposed under the conductive patterns and the variable resistivity material pattern so as to be electrically connected to another pattern of the conductive patterns. The variable resistivity material pattern is a phase-changeable material (e.g., a chalcogenide material) whose crystallization state is changed depending on applied heat (or energy).
Preferably, the upper metal interconnection is electrically connected to one conductive pattern through an upper contact plug. The upper contact plug penetrates an upper insulating layer disposed on the conductive patterns and the variable resistivity material pattern. Preferably, the impurity diffusion region is electrically connected to the other conductive pattern through a lower contact plug. The lower contact plug penetrates a lower insulating layer disposed under the conductive patterns and the variable resistivity material pattern.
In some embodiments, the phase-changeable memory device includes the other impurity diffusion region, a gate line, and a common drain electrode. The other impurity diffusion region is apart from the impurity diffusion region to which the lower contact plug is connected. The gate line is disposed on a semiconductor substrate between the impurity diffusion region and the other impurity diffusion region, and in the lower insulating layer. The common drain electrode is disposed in the lower insulating layer and is electrically connected to the other impurity diffusion region through a predetermined region of the lower insulating layer. When currents flow between the upper metal interconnection and the common drain electrode, a crystallization structure of a variable resistivity material at the active contact areas is changed in response to a density of the currents flowing across the active contact areas. For example, if predetermined currents are supplied in a state of grounding the upper metal interconnection and applying a turn-on voltage to the gate line, the heat (or energy) is applied to the active contact areas and, thus, the crystallization structure at the active contact areas is changed. By doing so, a program operation is performed. A read operation is performed by grounding the common drain electrode and applying a read voltage to the upper metal interconnection to detect resistance of the variable resistivity material pattern.
In some embodiments, the conductive patterns comprise titanium nitride. Each of the lower contact plug and the upper contact plug may respectively comprise titanium, titanium nitride and tungsten, which are sequentially stacked.
In accordance with further embodiments of the present invention, a phase-changeable memory device includes a phase-changeable material pattern, a pair of conductive patterns, an upper insulating layer, a bit line, a lower insulating layer, and a semiconductor substrate. The conductive patterns are disposed on the same plane as the phase-changeable material pattern and are in direct contact with the phase-changeable material pattern at active contact areas. The upper insulating layer is disposed on the phase-changeable material pattern and the conductive patterns. The bit line is disposed on the upper insulating layer and is electrically connected to one conductive pattern through an upper contact plug penetrating the upper insulating layer. The lower insulating layer is disposed under the phase-changeable material pattern and the conductive patterns. The semiconductor substrate includes a source region that is electrically connected to the other conductive pattern through a lower contact plug penetrating the lower insulating layer.
In some embodiments, the phase-changeable memory device includes a drain region, a gate line, and a common drain electrode. The drain region is apart from the source region to be formed in the semiconductor substrate. The gate line is disposed on a semiconductor substrate between the source and drain regions. The common drain electrode is disposed in the lower insulating layer and is electrically connected to the drain region through a predetermined region of the lower insulating layer.
In accordance with still other aspects of the present invention, a phase-changeable memory device includes a phase-changeable material pattern, a first electrode pattern, a second electrode pattern, resistance detection interconnection and a semiconductor substrate. The first electrode pattern is disposed on the same plane as the phase-changeable material pattern and is in contact with the phase-changeable material pattern at one active contact area. The second electrode pattern is disposed on the same plane as the phase-changeable material pattern and is in contact with the phase-changeable material pattern at another active contact area. Also, the second electrode pattern is formed symmetrically in mirror-image relations with respect to the first electrode pattern. The resistance detection interconnection is electrically connected to the first electrode pattern. The semiconductor substrate has an impurity diffusion region that is electrically connected to the second electrode pattern.
In some embodiments, an upper insulating layer is interposed between the phase-changeable material pattern and the resistance detection interconnection and between electrode patterns and the resistance detection interconnection. The resistance detection interconnection is electrically connected to the second electrode pattern through an upper contact plug penetrating the upper insulating layer. A lower insulating layer is interposed between the phase-changeable material pattern and the semiconductor substrate and between electrode patterns and the semiconductor substrate. The impurity diffusion region is electrically connected to the first electrode pattern through a lower contact plug penetrating the lower insulating layer. The resistance detection interconnection detects resistivity of the phase-changeable material pattern to provide information about a logic value.
In phase-changeable memory devices according to further embodiments of the present invention, each electrode pattern includes a plug contact region contacting a contact plug, and a material pattern contact region protruding from a middle portion of sidewalls of plug contact region toward the phase-changeable material pattern to contact the phase-changeable material pattern at an active contact area. A width of the material pattern contact region is preferably less than a thickness thereof. Accordingly, it is possible to reduce dimensions of the active contact areas.
According to further embodiments of the present invention, a memory device can be formed with an active contact area that is not defined by a contact plug process. The active contact area is formed at a side surface of a variable resistivity material pattern. Accordingly, a size of the active contact area is dependant upon a thickness of a conductive pattern contacting with the active contact area. The thickness of the conductive pattern can be thinner to decrease the size of the active contact area. According to further embodiments of the present invention, a memory device having two active contact areas can be provided. The active contact areas may be symmetrically formed at both sides of a variable resistivity material layer pattern.
In accordance with yet further embodiments of the present invention, there are provided methods of forming phase-changeable memory devices. A semiconductor substrate is formed with an impurity diffusion region. A conductive layer is formed that is electrically connected to the impurity diffusion region. Next, the conductive layer is patterned to form a symmetrical pair of conductive patterns so that one conductive pattern is electrically connected to the impurity diffusion region. A variable resistor pattern is then formed between the pair of conductive patterns. The variable resistor pattern direct contacts sidewalls of the conductive patterns at active contact areas. A metal interconnection is formed to be electrically connected to the other conductive pattern.
The pair of conductive patterns can be formed by following steps according to some embodiments. The conductive layer is patterned to form a intermediate conductive pattern so as to be electrically connected to the impurity diffusion region. Next, an insulating layer is formed on the resultant structure having the intermediate conductive pattern. Thereafter, the insulating layer and the intermediate conductive pattern are patterned to form the conductive patterns so that the intermediate conductive pattern is apart from the pair of conductive patterns. The insulating layer and the intermediate conductive pattern are patterned to form the variable resistivity resistor material layer over the insulating layer, at a space between the pair of conductive patterns. Thereafter, the variable resistivity material layer is patterned to form the variable resistivity material pattern.
The pair of the conductive pattern can be formed by forming an insulating layer on the conductive layer and patterning the insulating layer and the conductive layer. The variable resistor material pattern may be formed by patterning the insulating layer and the intermediate conductive pattern, forming the variable resistor material layer over the insulating layer at a space between the pair of conductive patterns, and patterning the variable resistor material layer.
In some embodiments, forming the conductive layer includes forming a lower insulating layer on the semiconductor substrate, patterning the lower insulating layer to form a lower contact hole exposing the impurity diffusion region, filling the contact hole to form a lower contact plug, and forming the conductive layer on the contact plug and the lower insulating layer. In further embodiments, forming the metal interconnection includes forming an upper insulating layer on the resultant structure with the variable resistor material pattern, patterning the upper insulating layer to form an upper contact hole which exposes the other conductive pattern that is not electrically connected to the impurity diffusion region, forming an upper contact plug filling the upper contact hole, forming a metal layer on the upper insulating layer and on the upper contact plug, and patterning the metal layer. In other embodiments, providing the semiconductor substrate includes forming another impurity diffusion region and a gate line to be positioned between the impurity diffusion region and another impurity diffusion region, forming a common drain electrode to be electrically connected to another impurity diffusion region.
In accordance with further embodiments of the present invention, there are provided methods of forming phase-changeable memory devices. A source region, a drain region and a gate electrode are formed on a semiconductor substrate. A common drain electrode is formed to be isolated from the semiconductor substrate by an insulating layer and to be electrically connected to the drain region through a predetermined region of the insulating layer. A lower insulating layer is formed on the resultant structure having the common drain electrode. A lower contact plug is formed in the lower insulating layer to be electrically connected to the source region. A phase-changeable material layer and a protective insulating layer are sequentially formed on the lower insulating layer and the lower contact plug. The protective insulating layer and the phase-changeable material layer are successively patterned to form a protective insulating pattern and a phase-changeable material pattern so as not to be in contact with the lower contact plug. A conductive layer is formed on the lower insulating layer, the lower contact plug and the patterns. Next, the conductive layer is patterned such that an upper portion of the phase-changeable material pattern is partially exposed, to form a pair of conductive patterns. The pair of conductive patterns is spaced apart from each other by the phase-changeable material pattern and in direct contact with both sidewalls of the phase-changeable material pattern. One conductive pattern is electrically connected to the lower contact plug. An upper insulating layer is formed on the lower insulating layer, the conductive patterns and the exposed phase-changeable material pattern. An upper contact plug is then formed to be electrically connected to the other conductive pattern that is not electrically connected to the lower contact plug. A metal interconnection is formed on the upper insulating layer to be electrically connected to the upper contact plug.
In accordance with further embodiments of the present invention, methods of forming phase-changeable memory devices are provided. A source region, a drain region and a gate electrode are formed at a semiconductor substrate. A common drain electrode is formed to be electrically connected to the drain region. A lower insulating layer is formed on the resultant structure having the common drain electrode. A lower contact plug is then formed in the lower insulating layer to be electrically connected to the source region. A conductive layer is formed on the lower insulating layer and the lower contact plug. The conductive layer is patterned to form a pair of conductive patterns, which are apart from each other, such that one conductive pattern is in contact with the lower contact plug. A chalcogenide material pattern is formed between the pair of conductive patterns so as to be directly contact with sidewalls of the pair of conductive patterns. An upper insulating layer is formed on the resultant structure having the material patterns. An upper contact plug is formed to be electrically connected to the other conductive pattern that is not electrically connected to the lower contact plug. A metal interconnection is formed on the upper insulating layer to be electrically connected to the upper contact plug.
The pair of conductive patterns may be formed by the following steps: The conductive layer is patterned to form an intermediate conductive pattern that is electrically connected to the lower contact plug. Next, an insulating layer is formed on the resultant structure where the intermediate conductive pattern will be formed. Thereafter, the insulating layer and the intermediate conductive pattern are patterned to the pair of conductive patterns. The chalcogenide material pattern may be formed by forming a chacogenide layer on the insulating layer and exposed lower insulating layer between the pair of conductive patterns, and patterning the chacogenide layer.